1. Field of the Invention
The present invention relates to a digital phase-locked loop (PLL) system provided in a playback apparatus, for example, a disk drive, and also to an N-phase clock phase error determination method used in the digital PLL system.
2. Description of the Related Art
As disclosed in, for example, Japanese Unexamined Patent Application Publication Nos. 11-341306 and 9-247137, a digital PLL system is used in a data recording/playback apparatus, such as a disk drive. For playback information read from, for example, a disk, a clock synchronized with the playback information is generated by a PLL circuit, and data is extracted as the playback information (radio frequency (RF) signal) by using this clock.
An example of the configuration of a digital-PLL data extraction system in a disk playback apparatus using, for example, a compact disc (CD) or a digital versatile disk (DVD), is shown in FIG. 84.
In the digital PLL system shown in FIG. 84, a playback RF signal generated by reflected light detected by an optical head of the disk playback apparatus is input, and then, run-length data is generated from the playback RF signal as playback information.
The RF signal is input into an asymmetry correction circuit 61 and is binarized therein. The binarized RF signal is then supplied to a master PLL control circuit 65. By using the binarized RF signal, the master PLL control circuit 65 generates a reference clock which is the same as the frequency of 1T of the RF signal, and outputs the reference clock to a voltage controlled oscillator (VCO) control circuit 66.
The VCO control circuit 66 controls a VCO 67 so that the oscillation frequency of the VCO 67 becomes equal to the reference clock. Under the control of the VCO control circuit 66, the clock (high frequency clock) is output from the VCO 67 as the oscillation output.
A frequency control circuit 68 receives the binarized RF signal and the high frequency clock from the VCO 67. The frequency control circuit 68 then performs sampling by using the binarized RF signal and the high frequency clock so as to detect a difference between the RF signal and the oscillation frequency of the VCO 67.
A phase-control/run-length-determination circuit 62 receives the binarized RF signal, the RF clock of the VCO 67, and a frequency deviation signal from the frequency control circuit 68. By using the frequency deviation signal and the binarized RF signal from the frequency control circuit 68, the phase-control/run-length-determination circuit 62 generates a channel clock synchronized with the RF signal, and then, extracts the run-length data from the RF signal by using this channel clock. The phase-control/run-length-determination circuit 62 also outputs a phase error.
The extracted run-length data and the phase error are supplied to a run-length correction circuit (hereinafter also referred to as the “RLL circuit”) 63. The RLL circuit 63 then corrects the run-length data according to the run-length data and the corresponding phase error. The corrected run-length data is supplied to a decode circuit system (not shown) at the subsequent stage.
The phase error is also supplied to a jitter meter 64, and the jitter meter 64 measures the jitter value by using the phase error.
The run-length data from the phase-control/run-length-determination circuit 62 is also supplied to the master PLL control circuit 65.
In the above-described known digital PLL system, the following problems are presented.
In the asymmetry correction circuit 61, it is important that the signal for slicing an analog RF signal be maintained at a correct level. In practice, however, external disturbances are imposed on the signal due to various factors, such as the characteristic of a signal source, the performance of the PLL system, noise in the transmission system, scratches or stains on physical recording media, for example, disk media, or physical reasons, for example, vibration, in which case, the slice level cannot be maintained at a correct level.
Conventionally, a system that feeds back the average of an input signal (RF signal) and setting the average as the slice level when performing asymmetry correction on the RF signal is implemented by an analog circuit. For example, an RF signal is input into a comparator 71 via a capacitor C and resistors R1 and R2, as shown in FIG. 85. The comparator 71 compares the RF signal with a slice level input from an amplifier 73, and outputs a binarized RF signal. The binarized RF signal is averaged in a low-pass filter 72, and is input into the comparator 71 via the amplifier 73 as the slice level.
According to this system, there is no problem when the quality of the input signal (RF signal) is high. However, if the level of the input signal deviates from a correct level due to, for example, an external disturbance, it is very difficult for the analog circuit to quickly respond to the signal deviation and to correct for such a deviation, since the source of the external disturbance is not known.
Additionally, the signal speed varies in a wide range even in the same system. This means that the response speed of the circuit must be controlled according to the signal speed even for the same type of external disturbance. In practice, it is very difficult to construct a system that can respond to such external disturbances by using an analog circuit, and effective measures have not been taken against various types of asymmetry deviations.
A known VCO is provided with only one control terminal. A change in the oscillation frequency with respect to the voltage in the VCO is shown in FIG. 86. In the diagram shown in FIG. 86, the horizontal axis represents the control voltage, while the vertical axis designates the oscillation frequency. In the VCO, the control voltage must oscillate the entire frequency range between VDD and VSS, in which case, the frequency sharply changes in accordance with the voltage change. The frequency change with respect to the voltage change can be represented by Δf1/ΔV in FIG. 86.
If the frequency change with respect to the voltage change is very large, a slight change in the control voltage due to, for example, noise, greatly changes the frequency, thereby influencing the playability (performance) of the circuit.
The time constant of a low-pass filter for the control voltage can be increased so as to suppress a very small change in the control voltage, thereby inhibiting the influence of noise. In this case, however, the oscillation frequency cannot be changed gently.
To lock a PLL with low jitter, the oscillation frequency must smoothly change with respect to a change in the control voltage of the VCO.
Accordingly, it can be considered that a plurality of VCOs optimal for the individual bands are provided and are selectively used. For example, FIG. 87 illustrates the frequency change (vertical axis) with respect to the voltage change (horizontal axis) when four VCOs, i.e., VCO-A, VCO-B, VCO-C, and VCO-D, are used.
The frequency characteristics of VCO-A, VCO-B, VCO-C, and VCO-D are represented by (a), (b), (c), and (d) of FIG. 87.
FIG. 87 shows that the frequency change with respect to the voltage change (Δf2/ΔV) is smaller than Δf1/ΔV shown in FIG. 86.
In this method, however, every time the playback speed of a disk medium is changed, the VCO must also be switched, thereby hampering the seamless operation.
In FIG. 87, for example, when the oscillation frequency is changed from 100 MHz to 200 MHz, the point (e) must be changed to the point (f), and thus, VCO-A must be changed to VCO-C, thereby hampering the seamless operation.
In the known digital PLL system shown in FIG. 84, in the frequency control circuit 68 and the phase-control/run-length determination circuit 62, the length of the RF signal is measured by using the high frequency clock obtained in the VCO 67. Accordingly, if there is a fluctuation in the oscillation frequency of the VCO 67, the length of the RF signal cannot be correctly measured, thereby significantly decreasing the playability.
It is desirable that the oscillation frequency of the VCO 67 changes linearly (Δf1/ΔV is constant) with respect to the voltage change, as shown in FIG. 86. In actuality, however, the oscillation frequency change is not linear with respect to the voltage change, as shown in FIG. 88, due to the circuit configuration or the process variations of the VCO. Accordingly, the frequency characteristic has a small gradient, such as Δf3/ΔV, and a large gradient, such as Δf4/ΔV, as shown in FIG. 88.
If noise is added to the control voltage at a portion of a large gradient, such as Δf4/ΔV, the oscillation frequency significantly changes.
Conventionally, no measure has been taken against the non-linearity of the frequency characteristic of the VCO by using a digital circuit.
The master PLL circuit 65 and the VCO control circuit 66 control the VCO 67 so that the oscillation frequency of the VCO 67 coincides with the frequency of 1T of the RF signal (4.3218 MHz×n(speed) for a CD, and 26.16 MHz×n(speed) for a DVD).
However, when a disk is started or if the disk is an eccentric disk, there is a temporal frequency deviation between the RF signal and the oscillation frequency of the VCO 67. There are two types of frequency deviations.
One type of frequency deviation occurs when the playback speed of a disk is significantly changed due to the start of the rotation of the disk or a long track jump. In this case, the RF signal and the VCO frequency, which are totally out of phase with each other (unlocking state), must be in phase with each other (locking state).
The other type of frequency deviation occurs because of an eccentric disk or a fluctuation of a spindle motor for rotating a disk. In the case of an eccentric disk, a frequency deviation occurs when the RF signal frequency gradually becomes out of phase with the VCO frequency. In the case of a fluctuation of the spindle motor, a frequency deviation occurs when motor-control wow flutter influences the length of the RF signal.
To handle such frequency deviations, a wide capture range and a lock range are provided for the PLL system, thereby ensuring a high level of linearity of the frequency characteristics.
When the above-described frequency deviation occurs, it must be detected in a certain way. Conventionally, a frequency deviation is detected by using only pulse length data generated by measuring a binarized RF signal with a high frequency clock.
However, if the pulse length data is 10.5T, it cannot be determined whether 10T measures more or 11T measures less. Accordingly, ambivalent pulse length data must be set to be a dead zone.
FIGS. 89A and 89B illustrate cases where the same frequency deviation occurs in different pulse lengths. In FIG. 89A, since the pulse length data measures, 5.25T, it can be determined that the pulse length data 5T measures more. In FIG. 89B, however, since the pulse length data measures, 10.5T, it cannot be determined whether the pulse data 10T measures more or 11T measures less.
FIGS. 89A and 89B show that the frequency deviation produces a greater influence larger pulse data, and thus, larger pulse data must have a longer dead zone.
However, if the dead zone is increased, the number of pulse length data from which frequency deviations can be recognized is decreased, thereby decreasing the speed in recognizing the frequency deviation.
In order to increase the range of frequency deviations that can be detected, small pulse length data from which frequency deviations can be correctly recognized must be used. The RF signal is, as shown in FIG. 90, an analog signal having certain gradients, and the amplitude varies according to the pulse length data. The small pulse length data is vulnerable to the influence of external disturbances since the amplitude of the RF signal is small. Thus, the reliability of measured frequency deviations also becomes low.
When playing back information according to a known technique, a channel clock synchronized with a binarized RF signal is generated in a digital PLL. The binarized RF signal and the channel clock are shown in (a) and (b) of FIG. 19. To match the phase and the frequency of the RF signal and the channel clock, the digital PLL scales the high frequency clock (Hif) by 7.5, 8.0, and 8.5 while also using the reverse edges of the high frequency clock (Hif) so as to lead or lag the phase, as shown in FIG. 20, thereby generating a channel clock.
The operating frequency of a digital PLL when playing back, for example, a DVD at ×1, is 209.28 MHz, which is 8 times as high as the channel clock 26.16 MHz required for ×1 DVD. The operating frequency of a digital PLL when playing back a DVD at ×20 is 4.185 GHz, which is 20 times as high as 209.28 MHz. It is difficult to generate a frequency of 4 GHz or higher by an existing CMOS process. Even if such a high frequency is generated, the fast operation increases power consumption, decreases the life of LSIs, or decreases the yield of LSIs since they do not satisfy the specifications.
For increasing the playability by using a known technique, the resolution of the channel clock can be increased. However, this further increases the frequency of the high frequency clock, and thus, fast playback operation cannot performed.
When playing back a CD or a DVD, run-length data which does not exist is sometimes read due to factors, such as noise, scratches on a disk, or a defective disk.
In the known RLL circuit 63, among data having an inversion interval of 3T to 11T, only data having a minimum inversion interval less than 3T is corrected, and corrections are conducted by comparing the level of run-length data before and after incorrect data or by comparing the level of phase errors. In this correction method, run-length data less than 3T is merely erased or expanded (for example, 2T, which does not exist, is expanded to 3T, which is the minimum inversion interval). Thus, correction is not based on the type of incorrect run-length data.
No considerations are taken for correcting continuous run-length data which does not comply with the format. Accordingly, the reliability of corrections is low.
Additionally, no corrections are conducted on run-length data exceeding 1T, and thus, drawbacks by such large run-length data cannot be overcome.
No considerations are taken for sync patterns, and a pseudo sync is sometimes generated accidentally by corrections, thereby decreasing the playability.
The jitter meter 64 in a known circuit generates a jitter value by determining whether the phase error measured with the high frequency clock is 0 or 1. This is because measurements of binary values are difficult due to a high operating frequency even if the playback speed of a disk is low. In the known jitter meter 64, measurements at a speed exceeding ×8 for a CD or ×1.6 for a DVD is not possible.
Additionally, phase errors are not directly used for determining a jitter value, and instead, they are merely replaced by a simple signal representing the presence or the absence of errors. Accordingly, there is no correlation between jitter values measured with a commercially available jitter meter and data output from the jitter meter 64.
As described above, there are various problems unique to known digital PLL systems, a digital PLL system that can solve the above-described problems and also a testing method for ensuring suitable operation in such a digital PLL system are demanded.